Role profiles
Semiconductors roles U.S. employers hire international talent for
Fab process, lithography, chip design and photonics as U.S. fabs ramp. Each profile describes the work, what employers screen for, and how a career like it maps to the O-1. These are role profiles, not job openings.
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Semiconductors listings
Each listing is modeled on a real U.S. posting; the employer is not named. Apply through O1DMatch to be matched with employers hiring for this kind of role.
Senior Photonics Engineer, Integrated Photonic Circuit Design and ModelingQuantum computing company building silicon photonic systems, Bay AreaPalo Alto, CA (Bay Area) · On-site · Full-timeUSD 139,800–164,300 base (Bay Area zone)O-1A fit (senior candidates)Added week of Nov 9, 2026Senior Manufacturing Engineer, Photonics Manufacturing & NPIQuantum computing company building silicon-photonics-based systems, Bay AreaMilpitas, CA (Bay Area) · On-site · Full-timeNot stated in the posting · BLS median for electrical and electronics engineers: USD 125,040O-1A fit (senior candidates)Added week of Nov 9, 2026Photonics Engineer, Photonic Integrated Circuit Design AutomationQuantum computing company building neutral-atom systems, Boston areaBoston, MA · On-site · Full-timeUSD 128k–208k base + equityO-1A fitAdded week of Nov 9, 2026Photonic Layout Engineer, Foundry Tapeout and PDKQuantum computing company building silicon photonic systems, Bay AreaPalo Alto, CA (Bay Area) · On-site · Full-timeUSD 139,800–164,300 base (Bay Area zone)O-1A fitAdded week of Nov 9, 2026Manager, Photonics Hardware Validation EngineeringQuantum computing company building silicon-photonics-based systems, Bay AreaMilpitas, CA (Bay Area) · On-site · Full-timeNot stated in the posting · BLS median for electrical and electronics engineers: USD 125,040O-1A fit (senior candidates)Added week of Nov 9, 2026Senior Process Integration Engineer, Photonic and Semiconductor DevicesGlobal semiconductor and display manufacturing equipment company, Bay AreaSanta Clara, CA (Bay Area) · On-site · Full-timeUSD 147k–202.5kO-1A fitAdded week of Nov 9, 2026Senior Process Engineer, PhotolithographyLeading-edge semiconductor wafer fabrication operation in Arizona; multiple openings for this rolePhoenix, AZ (Southwest) · On-site · Full-timeNot stated in the posting · BLS median for physicists: USD 166,880O-1A fit (senior candidates)Added week of Nov 9, 2026Senior Lithography Process Engineer, 300mm FabPublicly traded (Nasdaq) power and sensing semiconductor maker serving automotive and industrial markets, 300mm fabHopewell Junction, NY (Northeast) · On-site · Full-timeUSD 147k–250k baseO-1A fit (senior candidates)Added week of Nov 9, 2026Senior Silicon Engineer, Custom AI Accelerator ProgramAI company organized as a public benefit corporation, building a new custom silicon team, Bay AreaSan Francisco, CA (Bay Area) · Hybrid · Full-timeUSD 320k–485k baseO-1A fit (senior candidates)Added week of Nov 2, 2026Senior Design Verification Engineer, Chip-Level Control and InitializationAI infrastructure company building its own dataflow AI accelerator chips and rack-scale systems, Bay AreaSan Jose, CA (Bay Area) · On-site · Full-timeUSD 120k–200k baseO-1A fitAdded week of Nov 2, 2026Principal Post-Silicon Validation Engineer, High-Speed IO and MemoryAI infrastructure company building its own dataflow AI accelerator chips and rack-scale systems, Bay AreaSan Jose, CA (Bay Area) · On-site · Full-timeUSD 180k–255k baseO-1A fit (senior candidates)Added week of Nov 2, 2026Principal DFT Engineer, AI Accelerator SoCAI infrastructure company building its own dataflow AI accelerator chips and rack-scale systemsAustin, TX / San Jose, CA (Bay Area) · On-site · Full-timeUSD 180k–255k baseO-1A fit (senior candidates)Added week of Nov 2, 2026Director, ASIC Design Verification, AI Inference ChipsAI inference infrastructure company designing its own dataflow chips and rack-scale systems, Bay AreaSan Jose, CA (Bay Area) · On-site · Full-timeUSD 270k–340k baseO-1A fit (senior candidates)Added week of Nov 2, 2026
Role families
O-1A
ASIC / VLSI Design Engineer (AI Accelerators)
Design the custom silicon behind AI: RTL, synthesis, place-and-route and timing closure at 7, 5 and…
O-1AEUV / DUV Lithography Engineer
Keep the most complex machines in manufacturing printing: scanner optimization, OPC and resist process windows for sub-5nm…
O-1AProcess Integration Engineer (Advanced Node)
Own front-end or back-end process modules on a sub-7nm line and push yield up while the new U.S. fabs…
O-1ASilicon Photonics Engineer
Design photonic integrated circuits for data-center interconnect, LiDAR, sensing and quantum…
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Code WORKWITHUS unlocks the O1DMatch Starter plan at no cost. The eligibility check is an AI review of your background, not a legal opinion.