Senior Silicon Engineer, Custom AI Accelerator Program
AI company organized as a public benefit corporation, building a new custom silicon team, Bay Area
| Employer | AI company organized as a public benefit corporation, building a new custom silicon team, Bay Area (not named) |
|---|---|
| Location | San Francisco, CA (Bay Area) · Hybrid |
| Type & level | Full-time · Senior |
| Pay | USD 320k–485k base Source: pay range stated in the source posting |
| Visa path | O-1A fit (senior candidates) |
| Role family | ASIC / VLSI Design Engineer (AI Accelerators) |
About the role
The company runs very large AI training and inference workloads and is now building an in-house custom silicon team alongside its chip partners. This role is one of a small group of domain experts covering front-end design, verification, physical design, test, analog, foundry, CAD or packaging. The hire shapes the program from specification through first-silicon bring-up.
What you'll do
- Take part in program strategy, specification and execution, and help set the technical bar for the chip.
- Write specifications and interface definitions that other teams design against, and keep them coherent as the architecture settles.
- Make and own directional calls on technology and IP selection, and on build versus buy versus license.
- Contribute domain-specific tradeoffs to architecture and microarchitecture discussions.
- Work with inference, performance, kernel and infrastructure teams on hardware-software co-design.
- Support first-silicon bring-up and debug, including issues that cross domain boundaries.
Requirements
- Deep hands-on expertise in at least one silicon domain, such as front-end design, pre-silicon verification, physical design, design for test, analog and mixed-signal, or packaging and integrity.
- Personal contribution to silicon that taped out and shipped, with ownership you can describe in detail.
- Working fluency in domains adjacent to your own.
- Experience with external partners such as ASIC houses, IP vendors, foundries or test partners, including reviewing their work.
- Track record of owning technical direction decisions, plus clear communication and comfort with high autonomy.
- Bachelor's degree or equivalent combination of education, training and experience.
Nice to have
- Experience on machine learning accelerators or other large high-bandwidth designs.
- Experience on a founding or early-stage silicon team, standing up flows or tooling from scratch.
- Experience with both partner-executed and fully in-house programs.
- Hardware-software co-design experience with compiler, kernel or runtime teams.
- Depth in memory subsystems, on-die interconnect, numerics or low-power design.
Pay & benefits
USD 320k–485k base. The posting mentions competitive compensation, optional equity donation matching, generous vacation and parental leave, and flexible working hours.
Pay source: pay range stated in the source posting. Market data, not an offer from O1DMatch.
Visa path
Engineers in this field often support an O-1A case with evidence such as patents, publications, shipped chips they led, critical roles at notable organizations, and high compensation. The posting states no citizenship restriction and says the employer offers visa support, though not for every role or candidate. An employer like this, or a U.S. agent, can file the petition. Approval depends on the individual's record.
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