Principal Post-Silicon Validation Engineer, High-Speed IO and Memory
AI infrastructure company building its own dataflow AI accelerator chips and rack-scale systems, Bay Area
| Employer | AI infrastructure company building its own dataflow AI accelerator chips and rack-scale systems, Bay Area (not named) |
|---|---|
| Location | San Jose, CA (Bay Area) · On-site |
| Type & level | Full-time · Principal |
| Pay | USD 180k–255k base Source: pay range stated in the source posting |
| Visa path | O-1A fit (senior candidates) |
| Role family | ASIC / VLSI Design Engineer (AI Accelerators) |
About the role
This principal role owns post-silicon bring-up, debug and validation of high-speed IO and memory subsystems on an AI accelerator platform. The engineer leads root-cause work across silicon, board and software from first power-on through field deployment, and feeds lessons back into pre-silicon verification.
What you'll do
- Own bring-up and validation of high-speed IO and memory subsystems, including characterization, stress testing and performance analysis.
- Prepare power-on readiness before first silicon, including debug infrastructure, tooling and contingency plans.
- Lead system-level debug to root cause across silicon, board and software layers.
- Work with design, firmware, verification and system teams to close issues and hold the bring-up schedule.
- Support customer engineering on deployment and RMA debug, and own validation sign-off for release.
- Build scripts and tooling that automate validation, debug and data analysis, and review SoC and board designs from a debug perspective.
Requirements
- M.S. in electrical engineering, computer science or a related field.
- 7+ years in post-silicon validation or system bring-up.
- Experience with two or more high-speed IO or memory protocols such as PCIe, Ethernet, HBM, CXL or UCIe.
- Proven ability to lead cross-functional debug to root cause and closure.
- Strong analytical skills for test development and data analysis.
- Scripting proficiency in Python and bash.
Nice to have
- Understanding of high-speed SerDes training and adaptation.
- Experience with mixed-signal IO design and validation.
- Hands-on lab work with oscilloscopes, protocol analyzers and BERTs.
- Experience with optical interconnect.
- Ability to read and debug C/C++.
Pay & benefits
USD 180k–255k base. The posting lists base salary plus equity and benefits, including 95% employee medical premium coverage, 77% for dependents, an HSA with employer contribution, dental, vision, disability and life insurance, FSA options and wellness perks.
Pay source: pay range stated in the source posting. Market data, not an offer from O1DMatch.
Visa path
Senior post-silicon validation engineers often support an O-1A case with evidence such as patents, publications, high compensation, and a critical role in bringing recognized silicon to production. The posting states no citizenship restriction. An employer like this or a U.S. agent can file the petition; approval is never certain and depends on the individual's record.
How to get matched
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