Senior Design Verification Engineer, Chip-Level Control and Initialization
AI infrastructure company building its own dataflow AI accelerator chips and rack-scale systems, Bay Area
| Employer | AI infrastructure company building its own dataflow AI accelerator chips and rack-scale systems, Bay Area (not named) |
|---|---|
| Location | San Jose, CA (Bay Area) · On-site |
| Type & level | Full-time · Senior |
| Pay | USD 120k–200k base Source: pay range stated in the source posting |
| Visa path | O-1A fit |
| Role family | ASIC / VLSI Design Engineer (AI Accelerators) |
About the role
This verification engineer works on an AI accelerator chip, focusing on chip-level control and initialization: sequencing, state transitions, clocking and recovery across subsystems. The role builds SystemVerilog and UVM environments and owns verification plans from first draft to closure, working with architects, RTL designers and firmware engineers.
What you'll do
- Write and run verification plans for chip-level control and initialization features.
- Build SystemVerilog and UVM environments with test sequences, checkers, assertions and functional coverage.
- Verify sequencing, dependencies, state transitions and recovery scenarios across several chip subsystems.
- Create directed and constrained-random tests that expose architectural and implementation corner cases.
- Debug simulation and regression failures and root-cause them with design teams.
- Analyze coverage and regression results to drive verification closure.
Requirements
- B.S. in computer science, computer engineering or a related field.
- 5+ years of relevant industry experience.
- Strong understanding of digital design, SoC architecture and verification methodology.
- Strong SystemVerilog and UVM proficiency.
- Experience with constrained-random verification, functional coverage and assertion-based verification.
- Scripting skills in Python, Perl, TCL or shell.
Nice to have
- Familiarity with clock-domain and reset-domain crossing concepts and verification methods.
- Fluency using AI tools for verification development and debug.
Pay & benefits
USD 120k–200k base. The posting lists base salary plus equity and benefits, including 95% employee medical premium coverage, 77% for dependents, an HSA with employer contribution, dental, vision, disability and life insurance, FSA options and wellness perks.
Pay source: pay range stated in the source posting. Market data, not an offer from O1DMatch.
Visa path
Chip verification engineers often support an O-1A case with evidence such as patents, publications, high compensation, contributions to shipped silicon, and a critical role on a recognized product. The posting states no citizenship restriction. An employer like this or a U.S. agent can file the petition; approval is never certain and depends on the individual's record.
How to get matched
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