Director, ASIC Design Verification, AI Inference Chips
AI inference infrastructure company designing its own dataflow chips and rack-scale systems, Bay Area
| Employer | AI inference infrastructure company designing its own dataflow chips and rack-scale systems, Bay Area (not named) |
|---|---|
| Location | San Jose, CA (Bay Area) · On-site |
| Type & level | Full-time · Director |
| Pay | USD 270k–340k base Source: pay range stated in the source posting |
| Visa path | O-1A fit (senior candidates) |
| Role family | ASIC / VLSI Design Engineer (AI Accelerators) |
About the role
The verification team checks the company's AI accelerator chips before tape-out, covering block, full-chip and gate-level benches, performance, coverage, emulation and FPGA prototyping. This director owns pre-silicon quality through tape-out and into first-silicon lab debug. The role also leads an experienced group of 8–10 engineers and decides how their verification environment evolves.
What you'll do
- Own functional and performance verification through tape-out, including coverage closure and delivery dates.
- Set verification architecture, strategy, schedules and sign-off criteria, and report readiness and risk to executives.
- Act as technical authority on testbench architecture and lead debug on the hardest failures.
- Lead, coach and grow principal-level engineers, including hiring, leveling and building technical leads.
- Introduce new methodologies, including AI-assisted verification workflows, and direct emulation and FPGA prototyping.
- Work with architecture, design, software, compiler and runtime teams, and support lab validation of first silicon.
Requirements
- BS in EE, CS or CE with 12+ years (or equivalent) in ASIC design verification.
- 5+ years managing verification engineers, including hiring and performance management of senior and principal staff.
- Full-cycle verification from planning through tape-out and production on a complex ASIC or large subsystem.
- Hands-on depth in SystemVerilog, SVA, Python and UVM, OVM or VMM.
- Silicon bring-up experience, including lab validation and root-causing first-silicon issues.
- Working knowledge of machine learning SoCs or CPU/GPU designs and strong communication skills.
Nice to have
- MS or PhD in EECS with 15+ years in verification.
- Multiple large chips led to silicon, and scaling a team through growth.
- Post-silicon functional validation and performance verification experience.
- Knowledge of PCIe, Ethernet, memory subsystems, advanced TSMC nodes and chiplets.
- Fluency with AI tools applied to verification and flow development.
Pay & benefits
USD 270k–340k base. The posting lists a base salary plus equity, 95% employer-paid employee medical premiums, 77% for dependents, an HSA with employer contribution, dental, vision, disability and life coverage, FSAs and wellness benefits.
Pay source: pay range stated in the source posting. Market data, not an offer from O1DMatch.
Visa path
Verification leaders often support an O-1A case with evidence such as leadership of chips taken to silicon, critical roles at notable companies, high compensation, patents or publications, and recognition from peers. The posting states no citizenship restriction. An employer like this, or a U.S. agent, can file the petition. Approval depends on the individual's record.
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