Principal DFT Engineer, AI Accelerator SoC
AI infrastructure company building its own dataflow AI accelerator chips and rack-scale systems
| Employer | AI infrastructure company building its own dataflow AI accelerator chips and rack-scale systems (not named) |
|---|---|
| Location | Austin, TX / San Jose, CA (Bay Area) · On-site |
| Type & level | Full-time · Principal |
| Pay | USD 180k–255k base Source: pay range stated in the source posting |
| Visa path | O-1A fit (senior candidates) |
| Role family | ASIC / VLSI Design Engineer (AI Accelerators) |
About the role
This hands-on principal role owns design-for-test for large hierarchical AI accelerator SoCs, from DFT architecture through ATPG, MBIST and silicon bring-up. The engineer builds the flows and automation that produce production test patterns and supports diagnosis and yield work once silicon returns.
What you'll do
- Define and implement block-level and SoC-level DFT architecture for large hierarchical chips.
- Develop and maintain ATPG flows for stuck-at, at-speed and advanced fault models.
- Write scripts to automate DFT insertion, ATPG, coverage analysis, pattern generation and debug.
- Maintain JTAG, IEEE 1500 and IEEE 1687 infrastructure for test and debug access.
- Generate production-quality ATPG and MBIST patterns and support their deployment to ATE.
- Work with STA and physical design teams on DFT timing closure, and support silicon diagnosis, yield analysis and test optimization.
Requirements
- B.S. in computer science, computer engineering or a related field.
- 10+ years of relevant industry experience.
- Deep understanding of scan insertion, scan compression, ATPG, MBIST, JTAG and hierarchical DFT.
- Hands-on experience with industry-standard DFT tool flows.
- Knowledge of advanced ATPG, silicon diagnosis and failure localization methods.
- Experience with STA constraints for DFT modes, SDF simulation, and Verilog/SystemVerilog simulators.
Nice to have
- Experience with ATE pattern deployment and silicon bring-up.
- Experience with multi-die or chiplet DFT, known-good-die test or die-to-die interface testing.
- Experience with large compute, AI accelerator or HPC SoCs.
Pay & benefits
USD 180k–255k base. The posting lists base salary plus equity and benefits, including 95% employee medical premium coverage, 77% for dependents, an HSA with employer contribution, dental, vision, disability and life insurance, FSA options and wellness perks.
Pay source: pay range stated in the source posting. Market data, not an offer from O1DMatch.
Visa path
Principal-level DFT engineers often support an O-1A case with evidence such as patents, publications, high compensation, and a leading role on recognized chip programs. The posting states no citizenship restriction. An employer like this or a U.S. agent can file the petition; approval is never certain and depends on the individual's record.
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