Photonic Layout Engineer, Foundry Tapeout and PDK
Quantum computing company building silicon photonic systems, Bay Area
| Employer | Quantum computing company building silicon photonic systems, Bay Area (not named) |
|---|---|
| Location | Palo Alto, CA (Bay Area) · On-site |
| Type & level | Full-time · Mid-level |
| Pay | USD 139,800–164,300 base (Bay Area zone) Source: pay range stated in the source posting |
| Visa path | O-1A fit |
| Role family | Silicon Photonics Engineer |
About the role
This role turns photonic circuit designs and process requirements into manufacturable layouts for foundry fabrication. It sits between hardware and design-enablement teams, and combines hands-on layout with scripting and verification. The work supports a silicon photonic quantum computer.
What you'll do
- Prepare and maintain photonic layouts, from single components to complex circuits with passive and active elements.
- Drive foundry tapeouts through physical verification, including DRC, LVS, fill and density checks.
- Build and maintain layout automation tools that improve quality and speed.
- Help develop the PDK by implementing and validating layout components and design rules.
- Write clear documentation and handoff packages for each tapeout.
- Work with teams across departments, sites and time zones.
Requirements
- Master's degree, PhD or equivalent in Electrical or Computer Engineering, Materials Science or Physics.
- About 2 years of work or research experience in integrated photonics and layout.
- Experience creating layouts for photonic integrated circuits.
- Experience with a photonic layout tool such as GDSFactory, Synopsys or Cadence.
- Strong Python skills for layout generation, automation or numerical analysis.
- Experience with Git and with silicon photonic foundry rules and tapeout workflows.
Nice to have
Pay & benefits
USD 139,800–164,300 base (Bay Area zone). Full-time roles are eligible for equity, health coverage, a 401(k) with company match, wellness and family support programs, life and disability insurance, paid leave, discretionary time off and an end-of-year shutdown. Some benefits depend on location and role.
Pay source: pay range stated in the source posting. Market data, not an offer from O1DMatch.
Visa path
Photonic layout and design engineers often build an O-1A case from publications, patents, tapeout track records, recognized tool or PDK contributions, and a high salary. The posting states no citizenship restriction. An employer like this, or a U.S. agent, can file the petition, and approval depends on the individual's evidence.
How to get matched
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This listing describes a real U.S. posting so you can see what employers ask for. O1DMatch does not represent that employer and does not hold this opening; applying matches you with employers hiring for this kind of role. No visa outcome is promised.