Senior Research Engineer, Chip Design Reinforcement Learning
AI research and safety company organized as a public benefit corporation, Bay Area
| Employer | AI research and safety company organized as a public benefit corporation, Bay Area (not named) |
|---|---|
| Location | San Francisco, CA (Bay Area) · Hybrid |
| Type & level | Full-time · Senior |
| Pay | USD 500k–850k base Source: pay range stated in the source posting |
| Visa path | O-1A fit |
| Role family | Foundation Model Research Scientist |
About the role
This role sits on a code-focused reinforcement learning team and aims to improve how well language models design silicon. Chip design is demanding and unforgiving, so the team turns real hardware design expertise into tasks and reward signals that models can learn from. Work feeds directly into research and production training runs.
What you'll do
- Design and build reinforcement learning environments and evaluations for agentic RTL generation.
- Create environments covering design verification, including formal methods, and physical design optimization.
- Address cross-cutting RL issues such as EDA tool latency and proxy rewards.
- Run experiments and help shape the team's research roadmap.
- Deliver finished work into research and production training runs.
- Collaborate with researchers and engineers across and outside the company.
Requirements
- Expertise in ASIC or FPGA design, including RTL, verification (UVM, formal, coverage-driven) and physical design.
- Familiarity with PPA optimization, DFT and ECOs.
- Fluency with industry EDA tools and processes.
- Experience taping out chips and taking a design from spec to silicon.
- Ability to balance research exploration with engineering implementation.
- Bachelor's degree or equivalent training or experience.
Nice to have
- Experience with reinforcement learning, evaluations or environments.
- Built tooling or automation around chip design flows.
- Worked on ML accelerators or high-performance compute hardware.
- Familiarity with high-level synthesis or architecture simulators.
Pay & benefits
USD 500k–850k base. The posting mentions competitive compensation, optional equity donation matching, generous vacation and parental leave, flexible working hours, and an office space. Staff are expected in the office at least 25 percent of the time.
Pay source: pay range stated in the source posting. Market data, not an offer from O1DMatch.
Visa path
Researchers and engineers in reinforcement learning and chip design commonly support an O-1A case with publications, patents, taped-out products, citations, peer review work, and evidence of a high salary or critical role. The posting states no citizenship restriction and says the employer offers visa sponsorship for some roles and candidates, with immigration counsel retained. An employer like this or a U.S. agent can file the petition, though outcomes depend on each person's evidence.
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- Upload your evidenceEach document is sorted under the criterion it supports, and your criteria map shows what is still missing.
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